In contrast to classic procedural code, data flow models allow to recognize parallelism in modeled algorithms on multiple levels. The recognized parallelism can then be exploited by certain types of hardware accelerators (e.g., GPU or FPGA). However, many classic compilation frameworks, such as LLVM, do not support structured intermediate representations for data flow models. Therefore, a novel approach by the LLVM MLIR framework is to provide a framework for building own intermediate representations rather than dictating a fixed intermediate representation.

The focus of this thesis is to implement a data flow intermediate representation in the LLVM MLIR framework. Therefore, basic knowledge in C++ is helpful. The concrete targeted data flow models are described through a novel data flow language. This language has been created to enable the effective compilation for a novel industrial hardware accelerator.

Keywords: LLVM MLIR, Compiler, Data Flow